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HY57V283220T-I/ hy5v22f-i 4 banks x 1m x 32bi t synchronous dram this document is a general product descrip tion and is subject to change without notice. hynix semiconductor inc. does not assum e any responsibility for use of circuits des cribed. no patent licenses are implied. rev. 0.6/nov. 02 description the hynix HY57V283220T-I / hy5v22f-i is a 134,217,728-bi t cmos synchronous dram, ideally suited for the mem- ory applications which require wide data i/o and high bandwidth. HY57V283220T-I / hy5v22f-i is organized as 4banks of 1,048,576x32. HY57V283220T-I / hy5v22f-i is offering fully synchronous oper ation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and outp ut voltage levels are compatible with lvttl. programmable options include the length of pipeline (read lat ency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a bu rst of read or write cycles in progre ss can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? jedec standard 3.3v power supply ? all device pins are compatible with lvttl interface ? 86tsop-ii, 90ball fbga with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of system clock ? data mask function by dqm0,1,2 and 3 ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ? burst read single write operation ordering information part no. clock frequency organization interface package hy57v283220(l)t-5i hy5v22(l)f-5i 200mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-55i hy5v22(l)f-55i 183mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-6i hy5v22(l)f-6i 166mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-7i hy5v22(l)f-7i 143mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-8i hy5v22(l)f-8i 125mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-pi hy5v22(l)f-pi 100mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga hy57v283220(l)t-si hy5v22(l)f-si 100mhz 4banks x 1mbits x32 lvttl 86tsop-ii 90ball fbga
rev. 0.6/nov. 02 2 HY57V283220T-I / hy5v22f-i pin configuration ( HY57V283220T-I series) v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v dd dqm0 /w e /c a s /r a s /c s a11 ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd nc dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 86pin tsop ii 400m il x 875m il 0.5m m pin pitch v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v dd dqm0 /w e /c a s /r a s /c s a11 ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd nc dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 nc v dd dqm0 /w e /c a s /r a s /c s a11 ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd nc dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 86pin tsop ii 400m il x 875m il 0.5m m pin pitch pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and wh en deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for in ternal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection
rev. 0.6/nov. 02 3 HY57V283220T-I / hy5v22f-i ball configuration ( hy5v22f-iseries) ball description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and wh en deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multiplexed data input / output pin v dd /v ss power supply/ground power supply for internal circuits and input buffers v ddq /v ssq data output power/ground power supply for output buffers nc no connection no connection top view a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /c as /w e dq m 0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456 top view a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /c as /w e dq m 0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456 a b c d e f g h j k l m n p r dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /c as /w e dq m 0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /c as /w e dq m 0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 dq26 dq24 vss dq28 vddq vssq vssq dq27 dq25 vssq dq29 dq30 vddq dq31 nc vss dqm3 a3 a4 a5 a6 a7 a8 nc clk cke a9 dqm1 nc nc vddq dq8 vss vssq dq10 dq9 vssq dq12 dq14 dq11 vddq vssq dq13 dq15 vss vdd dq23 dq21 vddq vssq dq19 dq22 dq20 vddq dq17 dq18 vddq nc dq16 vssq a2 dqm2 vdd a10 a0 a1 nc ba1 a11 ba0 /cs /ras /c as /w e dq m 0 vdd dq7 vssq dq6 dq5 vddq dq1 dq3 vddq vddq vssq dq4 vdd dq0 dq2 123 789 456
rev. 0.6/nov. 02 4 HY57V283220T-I / hy5v22f-i functional block diagram 1mbit x 4banks x 32 i/o synchronous dram x decoder state machine a0 a1 a11 ba0 ba1 address buffers address register mode register row pre decoder column pre decoder column add counter row active column active burst counter data out control cas latency refresh counter dq0 dq1 dq30 dq31 self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we dqm0 dqm1 dqm2 dqm3 x32 bank 3 x decoder x decoder memory cell array y decoder x decoder 1m x32 bank 0 1m x32 bank 1 1m x32 bank 2 1m x decoder x decoder state machine a0 a1 a11 ba0 ba1 address buffers address register mode register row pre decoder column pre decoder column add counter row active column active burst counter data out control cas latency refresh counter dq0 dq1 dq30 dq31 self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we dqm0 dqm1 dqm2 dqm3 x32 bank 3 x decoder x decoder x decoder x decoder memory cell array y decoder x decoder memory cell array y decoder x decoder 1m x32 bank 0 1m x32 bank 1 1m x32 bank 2 1m
rev. 0.6/nov. 02 5 HY57V283220T-I / hy5v22f-i absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta=-40 to 85 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration with no input clamp diodes 3.v il (min) is acceptable -2.0v ac pulse width with 3 ns of duration with no input clamp diodes ac operating condition (ta=-40 to 85 c , 3.0v v dd 3.6v, v ss =0v - note1) note : 1.output load to measure access times is equiva lent to two ttl gates and one capacitor (30pf) for details, refer to ac/dc output load circuit parameter symbol rating unit ambient temperature t a -40 ~ 85 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.135 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il v ssq - 0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 30 pf 1
rev. 0.6/nov. 02 6 HY57V283220T-I / hy5v22f-i capacitance ( HY57V283220T-I series) (ta=25 c , f=1mhz, vdd=3.3v) output load circuit dc characteristics i (dc operating conditions unless otherwise noted) note : 1.v in = 0 to 3.6v, all other pins are not under test = 0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 2.5 4.0 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , dqm0~3 ci 2 2.5 4.0 pf data input / output capacitance dq0 ~ dq31 c i/o 4.0 6.5 pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4vi ol = +2ma vtt=1.4v rt=500 ? 30pf output dc output load circuit ac output load circuit vtt=1.4v rt=50 ? 30pf output z0 = 50 ?
rev. 0.6/nov. 02 7 HY57V283220T-I / hy5v22f-i dc characteristics ii (dc operating conditions unless otherwise noted) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specifie d values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.hy57v283220t(hy5v22f)-5i/55i/6i/7i/8i/pi/si 4.hy57v283220lt(hy5v22lf)-5i/55i/6i/7i/8i/pi/si parameter symbol test condition speed unit note -5 -55 -6 -7 -8 -p s operating current idd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 120 120 110 100 100 90 90 ma 1 precharge standby current in power down mode idd2p cke v il (max), t ck = 10ns 2 ma idd2ps cke v il (max), t ck = 1 precharge standby current in non power down mode idd2n cke v ih (min), cs v ih (min), t ck = 10ns input signals are changed one time during 2clks. all other pins vdd-0.2v or 0.2v 14 ma idd2ns cke v ih (min), t ck = input signals are stable. 9 active standby current in power down mode idd3p cke v il (max), t ck = 10ns 7 ma idd3ps cke v il (max), t ck = 6 active standby current in non power down mode idd3n cke v ih (min), cs v ih (min), t ck = 10ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 17 ma idd3ns cke v ih (min), t ck = input signals are stable. 13 burst mode operating current idd4 t t ck t ck (min), i ol =0ma all banks active cl=3 230 220 200 180 150 130 130 ma 1 cl=2 - - - - - 130 130 auto refresh current idd5 t rc t rc (min), all banks active 170 160 150 140 140 140 140 ma 2 self refresh current idd6 cke 0.2v 2 ma 3 0.8 4
rev. 0.6/nov. 02 8 HY57V283220T-I / hy5v22f-i ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.data-out hold time to be measured under 30pf load condition, without vt termination parameter symbol -5 -55 -6 -7 -8 -p -s unit note min max min max min max min max min max min max min max system clock cycle time cas latency = 3 tck3 5 1000 5.5 1000 6 1000 7 1000 8 1000 10 1000 10 1000 ns cas latency = 2 tck2 10 10 10 10 -10 10 12 ns clock high pulse width tchw 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1 clock low pulse width tclw 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1 access time from clock cas latency = 3 tac3 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns 2 cas latency = 2tac2 -6-6-6-6-6-6-6ns data-out hold time toh 1.5 - 2 - 2 - 2 - 2 - 2 - 2 - ns 3 data-input setup time tds 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 data-input hold time tdh 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1 address setup time tas 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 address hold time tah 1-1-1-1-1-1-1-ns1 cke setup time tcks 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 cke hold time tckh 1-1-1-1-1-1-1-ns1 command setup time tcs 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1 command hold time tch 1-1-1-1-1-1-1-ns1 clk to data output in low z-time tolz 1-1-1-1-1-1-1-ns clk to data output in high z-time cas latency = 3 tohz3 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns cas latency = 2tohz2 -6-6-6-6-6-6-6ns
rev. 0.6/nov. 02 9 HY57V283220T-I / hy5v22f-i ac characteristics ii (ac operating conditions unless otherwise noted) parameter symbol -5 -55 -6 -7 -8 -p -s unit not e min max min max min max min max min max min max min max ras cycle time operation trc 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns auto refresh trrc 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns ras to cas delay trcd 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns ras active time tras 38.7 100 k 38.7 100 k 42 100 k 42 100 k 48 100 k 50 100 k 50 100 k ns ras precharge time trp 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns ras to ras bank active delay trrd 2 - 2 - 2 - 2 - 2 - 20 - 20 - clk cas to cas delay tccd 1-1-1-1-1-1-1-clk write command to data-in delay twtl 0 - 0 - 0 - 0 - 0 - 0 - 0 - clk data-in to precharge command tdpl 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk data-in to active command tdal 4-4-4-4-4-4-4-clk dqm to data-out hi-z tdqz 2 - 2 - 2 - 2 - 2 - 2 - 2 - clk dqm to data-in mask tdqm 0-0-0-0-0-0-0-clk mrs to new command tmrd 2-2-2-2-2-2-2-clk precharge to data output hi-z cas latency = 3tproz33-3-3-3-3-3-3-clk cas latency = 2tproz22-2-2-2-2-2-2-clk power down exit time tpde 1-1-1-1-1-1-1-clk self refresh exit time tsre 1-1-1-1-1-1-1-clk1 refresh time tref -64-64-64-64-64-64-64ms note : 1. a new command can be given trrc after self refresh exit
rev. 0.6/nov. 02 10 HY57V283220T-I / hy5v22f-i device operating option table hy5xxxxxxxxx-5i hy5xxxxxxxxx-55 i hy5xxxxxxxxx-6 i hy5xxxxxxxxx-7 i hy5xxxxxxxxx-8i hy5xxxxxxxxx-pi cas latency trcd tras trc trp tac toh 200mhz(5ns) 3clks 3clks 8clks 11clks 3clks 4.5ns 1.5ns 183mhz(5.5ns) 3clks 3clks 8clks 10clks 3clks 5ns 2ns 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns cas latency trcd tras trc trp tac toh 183mhz(5.5ns) 3clks 3clks 7clks 10clks 3clks 5ns 2ns 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.5ns 2ns cas latency trcd tras trc trp tac toh 166mhz(6ns) 3clks 3clks 7clks 10clks 3clks 5.5ns 2ns 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.5ns 2ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 143mhz(7ns) 3clks 3clks 6clks 9clks 3clks 5.5ns 2ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2ns cas latency trcd tras trc trp tac toh 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 2ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2ns 83mhz(12ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 2ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.5ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.5ns
rev. 0.6/nov. 02 11 HY57V283220T-I / hy5v22f-i cas latency trcd tras trc trp tac toh 100mhz(10ns) 3clks 2clks 5clks 7clks 2clks 6ns 2ns 83mhz(12ns) 2clks 2clks 5clks 7clks 2clks 6ns 2.5ns 66mhz(15ns) 2clks 2clks 4clks 6clks 2clks 6ns 2.5ns hy5xxxxxxxxx-si
rev. 0.6/nov. 02 12 HY57V283220T-I / hy5v22f-i command truth table note : 1. exiting self refresh occurs by asynch ronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, opcode = operand code, nop = no operation 3. the burst read sigle write mode is entered by programming the write burst mode bit (a9) in the mode register to a logic 1. command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read h x lhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x llllx a9 pin high (other pins op code) 3 self refresh 1 entry h l l l l h x x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
rev. 0.6/nov. 02 13 HY57V283220T-I / hy5v22f-i 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) unit : mm(inch) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) 0.21(0.008) 0.18(0.007) package information (HY57V283220T-I series) 400mil 86pin thin small outline package
rev. 0.6/nov. 02 14 HY57V283220T-I / hy5v22f-i package information (hy5v22f-i series) 90ball fbga with 0.8mm of pin pitch 8.00 .10 8.00 .10

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